4-line bus-port esd-protection VBUS054B-HSF vishay semiconductors document number: 81624 for technical questions, contact: esdprotection@vishay.com www.vishay.com rev. 1.6, 21-oct-10 1 marking (example only) dot = pin 1 marking xx = date code yy = type code (see table below) features ? ultra compact llp75-6l package ? low package height < 0.6 mm ? 4-line usb esd-protection ? low leakage current ? low load capacitance c d = 0.8 pf ? esd-protection acc. iec 61000-4-2 15 kv contact discharge 15 kv air discharge ? e4 - precious metal (e.g. ag, au, nipd, nipdau) (no sn) ? compliant to rohs directive 2002/95/ec and in accordance to weee 2002/96/ec 20453 1 20397 6 4 5 1 2 3 21001 xx yy ordering information device name ordering code taped units per reel (8 mm tape on 7" reel) minimum order quantity VBUS054B-HSF VBUS054B-HSF-gs08 3000 15 000 package data device name package name type code weight molding compound flammability rating moisture sensitivity level soldering conditions VBUS054B-HSF llp75-6l u3 4.2 mg ul 94 v-0 msl level 1 (according j-std-020) 260 c/10 s at terminals absolute maximum ratings parameter test conditions symbol value unit peak pulse current pin 1, 3, 4 or 6 to pin 2 acc. iec 61000-4-5; t p = 8/20 s; single shot i ppm 3a pin 5 to pin 2 acc. iec 61000-4-5; t p = 8/20 s; single shot i ppm 10 a peak pulse power pin 1, 3, 4 or 6 to pin 2 acc. iec 61000-4-5; t p = 8/20 s; single shot p pp 45 w pin 5 to pin 2 acc. iec 61000-4-5; t p = 8/20 s; single shot p pp 200 w esd immunity contact discharge acc. iec61000-4-2; 10 pulses v esd 15 kv air discharge acc. iec61000-4-2; 10 pulses v esd 15 kv operating temperature junction temperature t j - 40 to + 125 c storage temperature t stg - 55 to + 150 c ** please see document vishay material category policy: www.vishay.com/doc?99902
VBUS054B-HSF vishay semiconductors 4-line bus-port esd-protection www.vishay.com for technical questions, contact: esdprotection@vishay.com document number: 81624 2 rev. 1.6, 21-oct-10 note ? ratings at 25 c, ambient temperature unless otherwise specified typical characteristics (t amb = 25 c, unless otherwise specified) fig. 1 - esd discharge current wave form acc. iec 61000-4-2 (330 /150 pf) fig. 2 - 8/20 s peak pulse current wave form acc. iec 61000-4-5 electrical characteristics VBUS054B-HSF parameter test conditions/re marks symbol min. typ. max. unit protection paths number of li ne which can be protected n lines --4lines reverse stand-off voltage at i r = 0.1 a, pin 1, 3, 4 or 6 to pin 2 v rwm 5--v reverse current at v in = v rwm = 5 v, pin 1, 3, 4 or 6 to pin 2 i r - < 0.01 0.1 a reverse breakdown voltage at i r = 1 ma, pin 5 to pin 2 v br 6.3 7.1 8 v at i r = 1 ma, pin 1, 3, 4 or 6 to pin 2 v br 6.9 7.9 8.7 v reverse clamping voltage at i pp = 3 a; pin 1, 3, 4 or 6 to pin 2; acc. iec 61000-4-5 v c --15v forward clamping voltage at i f = 3 a; pin 2 to pin 1, 3, 4 or 6; acc. iec 61000-4-5 v f --5v capacitance pin 1, 3, 4 or 6 to pin 2 v in (at pin 1, 3, 4 or 6) = 0 v and v bus (at pin 5) = 5 v; f = 1 mhz c d -0.81pf pin 1, 3, 4 or 6 to pin 2 v in (at pin 1, 3, 4 or 6) = 2.5 v and v bus (at pin 5) = 5 v; f = 1 mhz c d -0.50.8pf line symmetry difference of the line capacitances dc d - - 0.05 pf supply line capacitance pin 5 to pin 2; at v r = 0; f = 1 mhz c zd - 110 - pf 0 % 20 % 40 % 60 % 8 0 % 100 % 120 % - 10 0 10 20 30 40 50 60 70 8 0 90 100 time (ns) discharge c u rrent i esd rise time = 0.7 ns to 1 ns 53 % 27 % 20557 0 % 20 % 40 % 60 % 8 0 % 100 % 010203040 time (s) i ppm 20 s to 50 % 8 s to 100 % 2054 8
VBUS054B-HSF 4-line bus-port esd-protection vishay semiconductors document number: 81624 for technical questions, contact: esdprotection@vishay.com www.vishay.com rev. 1.6, 21-oct-10 3 fig. 3 - typical input capacitance c in at pin 1, 3, 4, or 6 vs. input voltage v in fig. 4 - typical forward current i f vs. forward voltage v f fig. 5 - typical reverse voltage v r vs. reverse current i r fig. 6 - typical peak clamping voltage v c vs. peak pulse current i pp fig. 7 - typical clampi ng performanc e at + 8 kv contact discharge (acc. iec 61000-4-2) fig. 8 - typical clamping performance at - 8 kv contact discharge (acc. iec 61000-4-2) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0. 8 0.9 1.0 0123456 v i n (v) c i n (pf) f = 1 mhz; v bus (at pin 5) = 5 v pin 1, 3, 4 or 6 to pin 2 20549 0.001 0.01 0.1 1 10 100 0.5 0.6 0.7 0. 8 0.9 1 1.1 1.2 v f (v) i f (ma) pin 2 to pin 1, 3, 4 or 6 pin 2 to pin 5 20550 0 1 2 3 4 5 6 7 8 9 0.01 0.1 1 10 100 1000 10000 i r (a) v r (v) pin 5 to pin 2 pin 1, 3, 4 or 6 to pin 2 20551 - 10 - 5 0 5 10 15 20 01234 i pp (a) v c (v) meas u red acc. iec 61000-4-5 ( 8 /20 s - w a v e form) pin 1, 3, 4 or 6 to pin 2 pin 2 to pin 1, 3, 4 or 6 pin 5 to pin 2 pin 2 to pin 5 v 20552 c - 20 0 20 40 60 8 0 100 120 - 10 0 10 20 30 40 50 60 70 8 090 t (ns) v c-esd (v) acc. iec 61000-4-2 + 8 kv contact discharge pin 1, 3, 4, 6 to pin 2 20553 - 160 - 140 - 120 - 100 - 8 0 - 60 - 40 - 20 0 20 - 10 0 10 20 30 40 50 60 70 8 090 t (ns) v c-esd (v) acc. iec 61000-4-2 - 8 kv contact discharge pin 1, 3, 4 or 6 to pin 2 20554
VBUS054B-HSF vishay semiconductors 4-line bus-port esd-protection www.vishay.com for technical questions, contact: esdprotection@vishay.com document number: 81624 4 rev. 1.6, 21-oct-10 fig. 9 - typical peak clamping voltage at esd contact discharge (acc. iec 61000-4-2) fig. 10 - typical peak clamping voltage at esd contact discharge (acc. iec 61000-4-2) application note with the VBUS054B-HSF a double, high speed usb-port or up to 4 other high speed signal or da ta lines can be protected against transient voltage signals. negative transients will be clamped close belo w the ground level while positive transients w ill be clamped close above the 5 v working range. an avalanche diode clamps the supply line (v bus at pin 5) to ground (pin 2). the high speed data lines, d 1+ , d 2+ , d 1- and d 2- , are connected to pin 1, 3, 4 and 6. as long as the signal voltage on the data lines is between the ground- and the v bus -level, the low capacitance pn-diodes offer a very high isolation to v bus , ground and to the other data lines. but as soon as any transient signal exceeds this working range, one of the pn-diodes starts working in th e forward mode and clamps the transient to ground or to the avalanche breakthrough voltage level of the z-diode between pin 5 and pin 2. - 250 - 200 - 150 - 100 - 50 0 50 100 150 200 0 5 10 15 20 v esd (kv) v c-esd (v) acc. iec 61000-4-2 contact discharge v c-esd pin 1, 3, 4 or 6 to pin 2 pin 2 to pin 1, 3, 4 or 6 20555 - 8 0 - 60 - 40 - 20 0 20 40 60 8 0 100 120 140 0 5 10 15 20 v esd (kv) v c-esd (v) acc. iec 61000-4-2 contact discharge v c-esd pin 5 to pin 2 pin 2 to pin 5 20556 t w i n u s b - p o r t d 2+ v bus g n d r e c e i v e r ic d 2- d 1+ d 1- 20399 6 4 5 1 2 3
VBUS054B-HSF 4-line bus-port esd-protection vishay semiconductors document number: 81624 for technical questions, contact: esdprotection@vishay.com www.vishay.com rev. 1.6, 21-oct-10 5 background knowledge: a zener- or avalanche diode is an ideal device for cutting or clamping voltage spikes or voltage transients down to low and uncritical voltage values. the breakthrough voltage can easily be adjusted by the chip-technology to any desired value within a wide range. up to about 6 v the zener-effect (tunnel-effect) is responsible for the breakthrough characteristic. above 6 v th e so-called avalanche-effect is re sponsible. this is a more a brupt breakthrough phenomenon. be cause of the typical z-shape of the current-voltage-curve of such diod es, these diodes are generally called z-diode (= zener or avalanche diodes). an equally important parameter for a protection diode is the esd- and surge-power that allows the diode to short current in the pulse to ground with out being destroyed. this requirement can be adjusted by the size of the silicon chip (crystal). the bigger the active area the higher the current t hat the diode can short to ground. but the active area is also responsible for the diode capacitance - the bigger the area the higher the capacitance. the dilemma is that a lot of applications require an effective protection against more then 8 kv esd while the capacitance must be lower then 5 pf! this is well out of the normal range of a z-diode. however, a protection diode with a low capacitance pn-diode (switching diode or junction di ode) in series with a z-diode, can fulf il both requirements simultaneously: low capacitance and high esd- and/or surge immunity become possible! a small signal (v pp < 100 mv) just sees the low capacitance of the pn-diode, while the big capacitance of the z-diode in series remains invisible. such a constellation with a z-diode and a small pn-diode (with low capacitance) in series (anti-serial) is a real unidirectional protection device. the clamping current can only flow in one direction (f orward) in the pn-diode. the reverse path is blocked. another pn-diode "opens" the back path so that the protection device becomes bi directional! because the clamping voltage levels in forward and reverse directions are different, such a protection device has a bi directional and as ymmetrical clamping behaviour ( bias ) just like a single z-diode. c d = 0.4 pf c tot d zd cz d = 110 pf 20400 20401 d zd i/o gnd 20404 d 1 zd d 2 i/o gnd
VBUS054B-HSF vishay semiconductors 4-line bus-port esd-protection www.vishay.com for technical questions, contact: esdprotection@vishay.com document number: 81624 6 rev. 1.6, 21-oct-10 one mode of use is, in the very first moment before any pulses have arrived, all three diodes are completely discharged (so the diode capacitances are empty of charge) the first signal pulse with an amplitude > 0.5 v will drive the upper pn-diode (d 1 ) in a forward direction and sees the empty capacitance of the z-diode (zd). depending on the duration of th is pulse and the pause to the next one the z-diodes capacitance can be charged up so that the next pulse sees a lower capacitance. after some pulses the big z-diode could be completely charged up so that the following pulses just see the small capacitance of both pn-diodes. for some application this can work perfectly..... for others applications the capacitance must be the same all the time from the first till the last pulse. for these applications the appropriate mode of use is to connect the z-diode to the supply voltage. in this mode the z-diode is charged up immediately by the supply voltage and both pn-diodes are always used in reverse. this keeps their capacitance at a minimum. d 1 zd d 2 i/o gnd 20405 d 1 zd d 2 i/o gnd v bus 20406
VBUS054B-HSF 4-line bus-port esd-protection vishay semiconductors document number: 81624 for technical questions, contact: esdprotection@vishay.com www.vishay.com rev. 1.6, 21-oct-10 7 package dimensions in millimeters (inches): llp75-6l 1.05 (0.041) 0.5 (0.020) 0.95 (0.037) heat sink 0.3 (0.012) 0.2 (0.00 8 ) 0.3 (0.012) 0.2 (0.00 8 ) 0.3 (0.012) 0.2 (0.00 8 ) 0.55 (0.022) 0.45 (0.01 8 ) 0.6 (0.024) 0.25 (0.010) 0.05 (0.002) 0 (0.000) 0.15 (0.006) 0.60 (0.023) 0.54 (0.021) 1.65 (0.065) 1.55 (0.061) 1.65 (0.065) 1.55 (0.061) pin 1 marking 0.5 (0.020) 0.5 (0.020) 0.3 (0.012) 0.3 (0.012) 0.15 (0.006) 0.15 (0.006) 0.5 (0.020) 0.5 (0.020) 1 (0.039) 0.25 (0.010) solder resist mask solder pad doc u ment no.:s 8 -v-3906.02-010 (4) re v . 4 - date: 21. march 2006 20454 created - date: 04. may 2005 foot print recommendation: 1 (0.039) 1 (0.039)
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